A memory module of a computing device, such as a PC or workstation, is commonly arranged in terms of ranks. A rank comprises that number of memory chips, which, in sum, provide that number of data lines which corresponds to the width of a bus used to store data in the memory module by, e.g., a controller or a chip set. Typically, the bus width amounts to 64 bits. A rank thus defines a 64 bit wide area in memory. Including an error correction code (ECC), a rank defines a 72 bit wide area.
There are memory chips, which are accessible by four (“×4”) or eight (“×8”) data lines for retrieving data stored in a respective memory array. Correspondingly, a rank comprises 16×4-chips or 8×8-chips (including the ECC: 18×4-chips or 9×8-chips). A double-sided memory module may then, e.g., comprise 1, 2, or 4 ranks.
In order to write to or read data from a memory module, each rank has a known unique rank address. There are at least two possibilities depending on the kind of connection between the controller or the chip set, and each of the memory chips.
According to a first implementation the controller has additional lines, which afford a connection to each of the memory ranks in parallel. A further chip select signal is necessary to address the respective chips of a desired rank. In this case, which is represented by semiconductor memory modules of type DDR1-DDR3 (DDR: double data rate), further pins are needed with respect to the connector of the memory module, which represents a disadvantage in view of space saving and current reduction.
According to a second implementation, each memory chip (package) is provided with, e.g., two additional balls of a ball grid array (BGA). Both additional balls, which are then hardwired on a DIMM (double inline memory module) together define a rank address, which the chip belongs to, e.g., one of the four rank numbers 0-3. Thus, when a write command is issued, it is driven along with a transferal of the corresponding rank address (0-3). However, recent efforts trying to reduce the number of balls on a chip package in order to reduce footprint and increase the storage density are disadvantageously counteracted by that solution.
To reduce the amount of wiring and/or number of balls or pins needed to address memory chips of a memory module with respect to a memory controller or a chip set, and to increase storage density and readout velocity of semiconductor memory modules are desirable.